The thermo-mechanical robustness of interconnect structures is a key reliability concern for integrated circuits. The miniaturization process, with the introduction of new processing routes, not always optimized from the mechanical point of view, along with the package/silicon interaction result in an increase of the thermal stresses whilst the use of new low-k materials, with degraded mechanical properties, makes it more and more difficult to predict their in-service behavior. This paper presents two techniques developed at CEIT-Tecnun for the assessment of the mechanical reliability of the interconnect structures (IC). The first one called Cross-Sectional Nanoindentation (CSN) focuses on the determination of the strength of the interfaces between the different materials in the IC layers. The second one is based on the ability of commercial piezo actuators to mimic the stress state induced in the IC layers by the packaging process. Experimental development of both techniques along with numerical modeling is presented, turning them into powerful sound tools.
