Flip-chip packages are produced by an
interconnection technique in which the active area of a chip is mounted by
various interconnecting materials on a multilayer substrate. While flip-chip
technologies have progressed rapidly and are now widely used, they present
special reliability concerns. A large thermal expansion mismatch between the
chip and the substrate increases the likelihood of fatigue failure in solder
joints under cyclic thermal loading. In addition, the thermal mismatch often
results in the delamination of interfaces between two materials, which
eventually leads to mechanical and/or electrical failure. In this paper piezo
actuators are used to mimic stresses during packaging assembly and in
operation. The test has been modeled using finite elements and the results show
that the level of stresses reached during packaging can be attained. Electronic
speckle-pattern interferometry (ESPI) was applied for noncontact, real-time
evaluation of the deformation. Failure analysis has been performed using an FIB
dual beam. Cracks extending from the bump edge through the structures under
study have been observed.
